1. Technical Field
The present invention relates generally to semiconductor structures, and more particularly, to methods of forming a gas dielectric structure for a semiconductor structure.
2. Related Art
In order to enhance semiconductor chip operational speed, semiconductor devices have been continuously scaled down in size. Unfortunately, as semiconductor device size is decreased, the capacitive coupling between conductors in a circuit tends to increase since the capacitive coupling is inversely proportional to the distance between the conductors. This coupling may ultimately limit the speed of the chip or otherwise inhibit proper chip operation if steps are not taken to reduce the capacitive coupling.
The capacitance between conductors is also dependent on the insulator, or dielectric, used to separate the conductors. Traditional semiconductor fabrication commonly employs silicon dioxide (SiO2) as a dielectric, which has a dielectric constant (k) of approximately 3.9. One challenge facing further development is finding materials with a lower dielectric constant that can be used between the conductors. As the dielectric constant of such materials is decreased, the speed of performance of the chip is increased. Some new low-k dielectric materials that have been used to provide a lower dielectric constant between conductors include, for example, fluorinated glass and organic materials. Unfortunately, provision of newer low-k dielectric materials presents a number of new challenges, which increase process complexity and cost.
Implementation of organic materials to reduce the dielectric constant also reduces the overall back-end-of-line (BEOL) capacitance. Unfortunately, organic materials suffer from temperature limitations, shrinkage or swelling during manufacturing or chip operation, and poor structural integrity. Instead of using SiO2 and organic materials, another approach is to implement gas, such as air, which is provided in the form of a gas dielectric structure in a semiconductor structure. Simple capacitance modeling of parallel wires shows that even a small air-gap near the wire results in a significant improvement in the overall dielectric constant (k) for a structure, e.g., a 10% air gap per edge will reduce the effective dielectric constant of a dielectric by approximately 15%. Current processing for implementing gas dielectric structure, however, is fairly complex and cannot be easily integrated into conventional damascene wire formation. Damascene wire formation is a process in which interconnect metal lines are delineated in dielectrics isolating them from each other following lithography and etching by means of chemical-mechanical planarization (CMP). In this process, an interconnect pattern is first lithographically defined in the layer of dielectric, metal is then deposited to fill resulting trenches and then excess metal is removed by means of chemical-mechanical polishing (planarization). Typically gas dielectric formation requires additional masking layers for reactive ion etching (RIE) processing steps relative to damascene wire formation. In addition, application of simple gas dielectric structures tends to create sagging of long line conductors as well as producing poor structural stability.
Accordingly, a need has developed in the art for an improved method of forming a gas dielectric structure for a semiconductor structure.